1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device. More particularly, the invention relates to a nonvolatile semiconductor memory device having a floating gate element.
2. Description of the Background Art
For example, Japanese Patent Laying-Open No. 11-17035 discloses a conventional nonvolatile semiconductor memory device. FIG. 28 is a plan view of the conventional nonvolatile semiconductor memory device disclosed in the publication. FIG. 29 is a cross section taken along line XXIXxe2x80x94XXIX of FIG. 28. FIG. 30 is a cross section taken along line XXXxe2x80x94XXX of FIG. 28. FIG. 31 is a cross section taken along line XXXIxe2x80x94XXXI of FIG. 28.
Referring to FIG. 28, a memory region 500 and a peripheral region 600 are formed on a silicon substrate 401. In the memory region 500, bit lines 420 extend so as to perpendicularly cross control gate electrodes 410. In peripheral region 600, a plurality of gate electrodes 434 are formed, and an isolation oxide film 430 is positioned between gate electrodes 434. Memory region 500 in which a memory transistor is formed and peripheral region 600 in which a transistor having gate electrode 434 is formed are electrically isolated from each other by an LOCOS (Local Oxidation of Silicon) film 449.
Referring to FIGS. 29 and 30, memory region 500 is shown by cross sections of regions 200 and 300. A memory transistor has n-type impurity regions 413a and 413b as drain regions, an n-type impurity region 414 as a source region, a silicon oxide film 404, a floating gate electrode 407, an ONO (Oxide Nitride Oxide) film 408, a silicon oxide film 409, and control gate electrode 410.
Impurity regions 413a and 413b and impurity region 414 are formed in the surface of p-type silicon substrate 401 with a predetermined distance from each other. Floating gate electrode 407 is formed on regions sandwiched by impurity regions 413a and 413b and impurity region 414 via silicon oxide film 404.
Control gate electrode 410 is formed so as to extend over floating gate electrode 407 via ONO film 408 consisting of three layers of a silicon oxide film, a silicon nitride film, and a silicon oxide film, and silicon oxide film 409.
On silicon substrate 401, a bottom n-well 402 and a p-well 403 in contact with bottom n-well 402 are formed. A trench 405 is formed between floating gates 407 arranged in a predetermined direction, and a silicon oxide film 406 is formed so as to fill trench 405.
The upper end face of silicon oxide film 406 is positioned between the top face and bottom face of floating gate electrode 407. On silicon oxide film 406 and floating gate electrode 407, ONO film 408, silicon oxide film 409, control gate electrode 410, and a TEOS (Tetra Ethyl Ortho Silicate) oxide film 411 are formed.
A p-type pocket region 415 is formed so as to surround impurity region 414. On side walls of floating gate electrode 407, ONO film 408, silicon oxide film 409, control gate electrode 410, and TEOS oxide film 411, a side wall oxide film 412 is formed.
An interlayer insulating film 416 is formed over silicon substrate 401 so as to cover the memory transistor. In a part of interlayer insulating film 416, contact holes 417 reaching impurity regions 413a and 413b are formed. A doped polysilicon layer 420a is formed so as to fill the contact holes 417 and cover interlayer insulating film 416.
Bit line 420 constructed by doped polysilicon layer 420a which is in contact with interlayer insulating film 416 and a tungsten silicide layer 420b is formed. An interlayer insulating film 421 is formed so as to cover interlayer insulating film 416 and bit line 420. A silicon oxide film 422 is formed on interlayer insulating film 421, and an aluminum interconnection 423 is formed so as to be buried in silicon oxide film 422. A smooth coat film 424 is formed so as to be in contact with silicon oxide film 422 and aluminum interconnection 423 and, further, an aluminum interconnection 425 is formed on smooth coat film 424.
Referring to FIG. 31, peripheral region 600 is expressed by a region 800 shown in FIG. 31. Isolation oxide film 430 is formed in silicon substrate 401. A p-well 431 and an n-well 432 are formed by using isolation oxide film 430 as a border.
On p-well 431, a transistor having gate electrode 434, a silicon oxide film 433, and an n-type low-density impurity region 437 and an n-type high-density impurity region 438 serving as source/drain regions is formed. On n-well 432, a transistor having gate electrode 434, silicon oxide film 433, and a p-type low-density impurity region 439 and a p-type high-density impurity region 440 serving as source/drain regions is formed. A silicon oxide film 435 is formed on gate electrode 434, and a side wall oxide film 436 is formed on the side walls of gate electrode 434 and silicon oxide film 435.
Interlayer insulating films 416 and 421 are formed so as to cover the transistors. Contact holes 441 reaching silicon substrate 401 are formed in interlayer insulating films 416 and 421. A plug 442 is formed so as to fill contact hole 441. Aluminum interconnection 423 is formed so as to be buried in silicon oxide film 422 and to be in contact with interlayer insulating film 421 and plug 442. Smooth coat film 424 is formed on silicon oxide film 442, and an aluminum interconnection 443 is formed so as to be buried in smooth coat film 424. Aluminum interconnection 425 which is in contact with aluminum interconnection 443 is formed on smooth coat film 424.
FIGS. 32 and 33 are cross sections showing fabricating processes of the nonvolatile semiconductor memory device illustrated in FIG. 30. Referring to FIG. 32, on silicon substrate 401, bottom n-well 402, p-well 403, a silicon oxide film 463, doped polysilicon 464, and an ONO film 466 are sequentially formed. A silicon oxide film, doped polysilicon, a tungsten silicide layer, and a TEOS oxide film are formed so as to cover ONO film 466. A resist is applied so as to cover the TEOS oxide film and patterned in a predetermined shape, thereby forming a resist pattern 469. By etching the TEOS oxide film, tungsten silicide layer, doped polysilicon, and silicon oxide film by using resist pattern 469 as a mask, TEOS oxide film 411, control gate electrode 410, and silicon oxide film 409 are formed. After that, resist pattern 469 is removed.
Referring to FIG. 33, the whole silicon substrate 401 is covered with a resist, and the resist is patterned in a predetermined shape, thereby forming a resist pattern 470. By etching ONO film 466, doped polysilicon 464, and silicon oxide film 463 along resist pattern 470, ONO film 408, floating gate electrode 407, and silicon oxide film 404 are formed. After that, resist pattern 470 is removed.
Impurity regions 413a and 413b, pocket region 415, side wall oxide film 412, interlayer insulating film 416, bit line 420, interlayer insulating film 421, aluminum interconnection 423, silicon oxide film 422, smooth coat film 424, and aluminum interconnection 425 are sequentially formed, thereby completing the nonvolatile semiconductor memory device shown in FIG. 30.
In the method of fabricating the nonvolatile semiconductor memory device as described above, as shown in FIG. 33, the memory gate in which floating gate electrode 407 and control gate electrode 410 are overlapped with each other has a vertically-long shape. In an etching process, etching of floating gate electrode 407 positioned in the lowest layer needs high-precision dimensional control. Since the memory gate itself has the vertically-long shape, there is a problem such that the dimensional control is difficult. It is also difficult to prevent accumulation of an etching residue between neighboring floating gates 407. Consequently, it is difficult to fabricate floating gate electrode 407 with high precision.
The cross section of FIG. 29 is a cross section in the direction of the channel width of floating gate electrode 407. As the nonvolatile semiconductor memory device becomes finer, the distance in the channel width direction between the neighboring floating gate electrodes 407 is also shortened. When the distance in the channel width direction is shortened, a so-called disturbance phenomenon such that writing operation is performed also on the floating gate electrodes adjacent to the floating gate electrode to which data is to be written occurs. The phenomenon is apt to occur in an AND type nonvolatile semiconductor memory device in which an isolation oxide film does not appear in the cross section in the channel width direction.
The invention has been achieved to solve the problems as described above.
An object of the invention is to provide a nonvolatile semiconductor memory device whose floating gate electrode can be fabricated with high precision.
Another object of the invention is to provide a nonvolatile semiconductor memory device in which the disturbance phenomenon can be effectively prevented.
A nonvolatile semiconductor memory device according to an aspect of the invention has a semiconductor substrate, and a floating gate electrode formed on the semiconductor substrate interposed a gate insulating film therebetween. The floating gate electrode includes a lower conductive layer formed on the gate insulating film and having a first width in a channel width direction, and an upper conductive layer formed on the lower conductive layer and having a second width wider than the first width in the channel width direction.
In the nonvolatile semiconductor memory device constructed as described above, the lower conductive layer on the gate insulating film has the first width narrower than the second width of the upper conductive layer in the channel width direction. Consequently, the distance between neighboring floating gate electrodes is increased in the portion of the lower conductive layer. As a result, the lower conductive layer and the floating gate electrode of another nonvolatile transistor are insulated from each other with reliability, so that the disturbance phenomenon can be prevented.
Preferably, the nonvolatile semiconductor memory device further includes a control gate electrode formed on the floating gate electrode interposed a dielectric film therebetween.
Preferably, the control gate electrode has a third width narrower than the second width.
Preferably, the nonvolatile semiconductor memory device further includes a side wall insulating layer formed on the dielectric film so as to be in contact with a side wall of the control gate electrode. The width of the side wall insulating layer is narrowed with distance from the dielectric film. In this case, since the side wall insulating layer is formed on the side wall of the control gate electrode, the control gate electrode can be insulated from other conductive layers with reliability.
Preferably, the nonvolatile semiconductor memory device further includes a side wall conductive layer formed on the dielectric film so as to be in contact with a side wall of the control gate electrode. The width of the side wall conductive layer is narrowed with distance from the dielectric film. In this case, the side wall conductive layer is in contact with the side wall of the control gate electrode, so that the side wall conductive layer also functions as a control gate electrode. As a result, the cross sectional area of the control gate electrode becomes large, and electric resistance of the control gate electrode can be reduced.
Preferably, the nonvolatile semiconductor memory device further includes a first insulating film formed on the semiconductor substrate. The top face of the first insulating film and the top face of the lower conductive layer are almost flush with each other. In this case, since the top face of the lower conductive layer and the top face of the first insulating film are flush with each other, an upper conductive layer can be easily formed on the top faces.
Preferably, the upper conductive layer and the lower conductive layer are made of the same material. In this case, the adhesion of the lower and upper conductive layers is improved, so that a very reliable nonvolatile semiconductor memory device can be provided.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.